library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Encoder8_3 is
port ( ENABLE: in STD_LOGIC;
D_IN: in STD_LOGIC_VECTOR(7 downto 0);
D_OUT: out STD_LOGIC_VECTOR(2 downto 0) );
end Encoder8_3;
architecture encoder_arch of encoder8_3 is
begin
process(ENABLE,D_IN)
begin
if ( ENABLE = '1') then
D_OUT <= "000";
Else
case D_IN is
when "00000001" => D_OUT <= "000";
when "0000001X " => D_OUT <= "001";
when "000001XX " => D_OUT <= "010";
when "00001XXX " => D_OUT <= "011";
when "0001XXXX " => D_OUT <= "100";
when "001XXXXX " => D_OUT <= "101";
when "01XXXXXX" => D_OUT <= "110";
when "1XXXXXXX" => D_OUT <= "111";
when others => NULL;
end case;
end if;
end process;
end encoder_arch;
