WRITE A VERILOG PROGRAM FOR 2 TO 4 DECODER

A decoder is a multiple input, multiple output logic circuit that converts coded inputs into coded outputs where the input and output codes are different. The enable inputs must be ON for the decoder to function, otherwise its outputs assumes a ‘disabled’ output code word. Decoding is necessary in applications such as data multiplexing, seven segment display and memory address decoding.

 

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

 

module decoder(a, y);

     input [1:0] a;

     output [3:0] y;

     reg [3:0] y;

always @ (a)

case(a)

2’b00: y<= 4’b1110;

2’b01: y<= 4’b1101;

2’b10: y<= 4’b1011;

2’b11: y<= 4’b0111;

end case;

endmodule