4 bitS gray to binary converter
entity GRAY_BINARY is
port( G: in std_logic_vector(3 downto 0);
b: INout std_logic_vector(3 downto 0));
end gray_BINARY;
architecture behavioral of gray_BINARY is
begin
b(3)<= G(3);
b(2)<= B(3) xor G(2);
b(1)<= B(2) xor G(1);
b(0)<= B(1) xor G(0);
end behavioral;
A demultiplexer is a circuit that receives information on a single line and transmits this information on one of 2 ^ N ouput lines.The selection of specific output lines is controlled by the value of N selection lines.The single input variable din as a path to all 4 outputs but the input information is directed to only one of the output lines.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Demux1_4 is
port ( d_in: in STD_LOGIC;
sel: in STD_LOGIC_VECTOR (1 downto 0);
d_out: out STD_LOGIC_VECTOR (3 downto 0));
end Demux1_4;
architecture demux1_4_arch of Demux1_4 is
begin
process(d_in,sel)
begin
d_out<="0000";
case sel is
when "00" => d_out(0)<=d_in;
when "01" => d_out(1)<=d_in;
when "10" => d_out(2)<=d_in;
when others => d_out(3)<=d_in;
end case;
end process;
end demux1_4_arch;
Verilog code for 1 to 4 demux
module demux(din, s, dout);
input din;
input [1:0] s;
output [3:0] dout;
reg [3:0] dout;
always @ (din or s)
case(s)
2’b00: dout(0)=din;
2’b01: dout(1)=din;
2’b10: dout(2)=din;
2’b11: dout(3)=din;
endcase
endmodule
H) N-Bit Comparator
Comparator is a special combinational circuit designed primarily to compare the relative magnitude of 2 binary numbers.It receives 2 N bit numbers A and B as inputs and the outputs are A>B,A=B and A
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity comparator is
Generic (N: integer := 3);
Port( A,B: in STD_LOGIC_VECTOR(N downto 0);
ALB,AGB,AEB: out STD_LOGIC);
end comparator;
architecture Comparator_arc of comparator is
begin
process(A,B)
begin
ALB<=’0’; AGB<=’0’; AEB<=’0’;
IF A=B THEN
AEB<=’1’;
ELSIF A>B THEN
AGB<=’1’;
ELSE
ALB<=’1’;
END IF;
end process;
end Comparator_arc;
Verilog Code for 4 bit comparator
module compare(a, b, aeqb, agtb, altb)
input [3:0] a, b;
output aeqb, agtb, altb;
reg aeqb, agtb, altb;
always @ (a or b)
if (a=b) aeqb=1’b1;
else if (a>b) agtb=1’b1;
else (a
endmodule
3. Write a HDL code to describe the functions of a full adder using three modeling styles.
A) STRUCTURAL modeling
àVHDL Code for the implementation of Half Adder
entity Halfadder is
Port ( A, B : in std_logic;
S, C : out std_logic); --sum& carry
end Halfadder;
architecture Behavioral of Halfadder is
begin
S <= A xor B;
C<= A and B;
end Behavioral;
àVHDL Code for Full Adder Using Component Instantiation Method.
entity FullAdder is
Port ( Ain : in std_logic;
Bin : in std_logic;
Cin : in std_logic;
Cout : out std_logic;
Sum : out std_logic);
end FullAdder;
architecture Behavioral of FullAdder is
Component Halfadder
Port ( A : in std_logic;
B: in std_logic;
S: out std_logic;
C: out std_logic);
end Component;
Signal temp1,temp2, temp3: std_logic;
begin
L1: Halfadder port
L2: Halfadder port
Cout <= temp2 or temp3;
end Behavioral;
B) Dataflow modeling
Architecture dataflow of fulladder is
Begin
Sum<= Ain XOR Bin XOR Cin;
Cout<= (Ain AND Bin) OR (Bin AND Cin) OR (Cin AND Ain);
End dataflow;
C) Behavioral modeling
Architecture behavior of fulladder is
Begin
Process(Ain,Bin,Cin)
Begin
Sum<= Ain XOR Bin XOR Cin;
Cout<= (Ain AND Bin) OR (Bin AND Cin) OR (Cin AND Ain);
End process;
End behavior;
4. Write a model for 32 - bit or 4-bit ALU using the schematic diagram shown below (example only)
· ALU should use combinational logic to calculate an output based on the fout bit op-code input.
· ALU should pass the result to the out bus when enable line is high and tri-state the out bus when the enable line is low.
· ALU should decode the 4 bit op-code according to the given in example below.
| Opcode | ALU Operation |
| 1 2 3 4 5 6 7 8 | A + B A – B A Compliment A * B A AND B A OR B A NAND B A XOR B |
-- This ALU is a combinational logic to calculate an output Based on the THREE bit Op-CODE INPUT.
-- ALU passes the result to the outPUT bus when enable line is low.
entity ALU is
Port ( A : in std_logic_vector(3 downto 0);
B : in std_logic_vector(3 downto 0);
Opcode : in std_logic_vector(2 downto 0);
enb : in std_logic;
OUTPUT : out std_logic_vector(3 downto 0);
oUTPUT1 : out std_logic_vector(7 downto 0));
end ALU;
architecture Behavioral of ALU is
begin
process(A,B,Opcode,enb)
begin
if enb= '1' then
case Opcode is
when "000" => oUTPUT<= A+B;
when "001" => oUTPUT<= A-B;
when "010" => oUTPUT<= not A;
when "011" => oUTPUT1<= A*B;
when "100" => oUTPUT<= A and B;
when "101" => oUTPUT<= A or B;
when "110" => oUTPUT<= A nand B;
when others =>oUTPUT<= A xor B;
end case;
else
oUTPUT <= (others =>'Z');
end if;
end process;
end Behavioral;
Sequential circuits
5. Develop the HDL code for the following flip-flops.
SR flip-flop: A SR flip - flop is the simplest possible memory element. The SR flip flop has two inputs Set and Reset. The SR flip-flop is a basic building block for other flip-flops.
D flip-flop: This is a flip - flop with a delay (D) equal to exactly equal to one cycle of the clock. The defect with SR FF is the indeterminate output when the data inputs at S and R are 1. In order to avoid this the input to R is through an inverter from S so that the input to R is always the complement of S and never same. The S input is redesignated as D.
JK flip-flop: The JK flip flop is called a “universal flip flop” because the other flip flops like D, SR, T can be derived from it. The “racing or race around condition” takes place in a JK FF when J=1 and K=1 and clock=1.
T flip-flop: T stands for toggling. It is obtained from JK FF by tying both the inputs J and K.
a) SR flip-flop
entity SRFF is
port ( s,R,CLK: in bit;
q: buffer std_logic ):=0;
end SRFF;
architecture s_r_ff_arch of SRFF is
begin
process(clk)
begin
if clk='1' and clk'event then
if(s='0' and r='0')then q<=q;
elsif(s='0' and r='1')then q<='0';
elsif(s='1' and r='0')then q<='1';
elsif (s='1' and r='1')then q<='Z';
end if;
end if;
end process;
end s_r_ff_arch;
b) D flip-flop
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DFF is
port (clk: in STD_LOGIC;
d: in STD_LOGIC;
q: out STD_LOGIC);
end DFF;
architecture d_ff_arch of DFF is
begin
process(clk)
begin
if(clk'event and clk='1')then
q<=d;
end if;
end process;
end d_ff_arch;
c) T flip-flop
entity tf is
Port ( clk,rst,t : in std_logic;
q:out std_logic;
qb:out std_logic);
end tf;
architecture Behavioral of tf is
signal temp:std_logic;
begin
process(clk,rst)
begin
if(rst='1')then
temp<='0';
elsif(clk='1' and clk'event)then
if(t='1')then
temp<=not temp;
end if;
end if;
end process;
q<=temp;
qb<=not temp;
end Behavioral;
d) JK flip-flop
entity jkff is
Port ( clk,rst,j,k : in std_logic;
q: out std_logic;
qb : out std_logic);
end jkff;
architecture Behavioral of jkff is
signal TEMP :std_logic;
begin
process(clk,rst)
variable jk:std_logic_vector(1 downto 0);
begin
if(rst='1')then
ff<='0';
elsif(clk='1' and clk'event)then
jk:=j & k;
case jk is
when "01"=>TEMP<='0';
when "10"=>TEMP<='1';
when "11"=>TEMP<=not TEMP;
when others=>TEMP<=TEMP;
end case;
end if;
end process;
q<=TEMP;
qb<=not TEMP;
end Behavioral;
6. Design 4-bit binary, BCD counters and “any sequence” counters.
a) 4-bit binary up counter
entity bincount is
Port ( clk,rst : in std_logic;
bincount: out std_logic_vector(3 downto 0));
end bincount;
architecture Behavioral of bincount is
signal bincount1:std_logic_vector(3 downto 0);
begin
process(clk,rst)
begin
if(rst='1')then
bincount1<=(others=>'0');
elsif(clk='1' and clk'event)then
if(bincount1="1111")then
bincount1<="0000";
else
bincount1<=bincount1+1;
end if;
end if;
end process;
bincount<=bincount1;
end Behavioral;
b) 4-bit binary down counter
entity bindown is
Port ( clk,rst : in std_logic;
bincount: out std_logic_vector(3 downto 0));
end bindown;
architecture Behavioral of bindown is
signal bincount1:std_logic_vector(3 downto 0);
begin
process(clk,rst)
begin
if(rst='1')then
bincount1<=(others=>'0');
elsif(clk='1' and clk'event)then
if(bincount1="0000")then
bincount1<="1111";
else
bincount1<=bincount1-1;
end if;
end if;
end process;
bincount<=bincount1;
end Behavioral;
c) 4-bit bcd up counter
entity bcdcount is
Port ( clk,rst : in std_logic;
bcdcount : out std_logic_vector(3 downto 0));
end bcdcount;
architecture Behavioral of bcdcount is
signal bcdcount1:std_logic_vector(3 downto 0);
begin
process(clk,rst)
begin
if(rst='1')then
bcdcount1<=(others=>'0');
elsif(clk='1' and clk'event)then
if(bcdcount1="1001")then
bcdcount1<="0000";
else
bcdcount1<=bcdcount1+1;
end if;
end if;
end process;
bcdcount<=bcdcount1;
end Behavioral;
c) 4-bit bcd down counter
entity bcddown is
Port ( clk,rst : in std_logic;
bcdcount : out std_logic_vector(3 downto 0));
end bcddown;
architecture Behavioral of bcddown is
signal bcdcount1:std_logic_vector(3 downto 0);
begin
process(clk,rst)
begin
if(rst='1')then
bcdcount1<=(others=>'0');
elsif(clk='1' and clk'event)then
if(bcdcount1="0000")then
bcdcount1<="1001";
else
bcdcount1<=bcdcount1-1;
end if;
end if;
end process;
bcdcount<=bcdcount1;
end Behavioral;
INTERFACING PROGRAMS
EXP1. Interface seven-segment LED to display BCD count starting from 0 to 9. There should be a delay of 1 sec between each count.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity seg7 is
Port ( clk : in std_logic;
a: out std_logic;
dout : out std_logic_vector (0 to 6));
end seg7;
architecture Behavioral of seg7 is
signal clk_div:std_logic_vector(22 downto 0);
signal clkd:std_logic;
type seg7 is array (0 to 9)of std_logic_vector(6 downto 0);
constant seg_value: seg7:=("1111110","0110000","1101101",
"1111001", "0110011","1011011","1011111",
"1110000","1111111","1110011");
begin
process(clk)
begin
if rising_edge (clk)then
clk_div<=clk_div+'1';
end if;
clkd<=clk_div(21);
end process;
process(clkd)
variable y: integer range
begin
if rising_edge(clkd) then
dout<=seg_value(y);
y:=y+1;
if y>9 then y:=0;
end if;
end if;
end process;
a<='1';
end behavioral;
Exp2: VHDL code for stepper motor to control the speed and direction.
entity stepper_motor is
Port ( d_out : out std_logic_vector(3 downto 0);
enb : in std_logic;
clk : in std_logic);
end stepper_motor;
architecture Behavioral of stepper_motor is
signal clk_div:std_logic_vector(12 downto 0);
signal clkd:std_logic;
signal step:std_logic_vector(3 downto 0):="1000";
begin
process(clk)
begin
if rising_edge(clk) then
clk_div<=clk_div+1;
end if;
clkd<=clk_div(12);
end process;
process(clkd)
begin
if rising_edge(clkd) then
if enb='1' then
step<=step(0) & step(3 downto 1);
elsif enb='0' then
step<=step(2 downto 0) & step(3);
end if;
end if;
end process;
d_out<=step;
end Behavioral;
Exp3: Interface LCD 16 X 2 to display following message “SHASHI”.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lcd_interface is
Port ( data : out std_logic_vector(7 downto 0);
reg_sel : out std_logic;
rd_wr : out std_logic;
en : out std_logic;
clk : in std_logic);
end lcd_interface;
architecture Behavioral of lcd_interface is
signal clk_div:std_logic_vector(21 downto 0);
signal clkd:std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
clk_div<=clk_div+1;
end if;
clkd<=clk_div(21);
en<=clk_div(21);
end process;
process(clkd)
variable a: integer range
type lcd_type is array(natural range
constant lcd_data:
lcd_type(0 to 6):=("00111000","00000001","00001110","00000010",
"01000111","01001100","01011111",”01000010”,”01000001”,”01001100”);
begin
rd_wr<='0';
if rising_edge(clkd) then
if a<4 then
reg_sel<='0';
data<=lcd_data(a);
else
reg_sel<='1';
data<=lcd_data(a);
end if;
a:=a+1;
end if;
end process;
end Behavioral;
Exp4. Interface keypad and seven-segment display, when the key is pressed the corresponding key number should be displayed using FPGA kit.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity keypad is
Port ( keyrow : out std_logic_vector(3 downto 0);
keycol :in std_logic_vector(3 downto 0);
a:out std_logic;
clk : in std_logic;
led_out : out std_logic_vector(0 to 6));
end keypad;
architecture Behavioral of keypad is
signal key_val:integer range
signal key_hit:std_logic;
signal key_scan:std_logic_vector(3 downto 0);
signal clk_div:std_logic_vector(6 downto 0);
signal clkd:std_logic;
begin
process(keycol)
begin
case keycol is
when "1110"=>key_hit<='1';
when "1101"=>key_hit<='1';
when "1011"=>key_hit<='1';
when "0111"=>key_hit<='1';
when others=>key_hit<='0';
end case;
end process;
process(key_hit)
begin
if rising_edge(key_hit) then
if (key_scan="1110" and keycol="1110") then key_val<=0;
elsif (key_scan="1110" and keycol="1101") then key_val<=1;
elsif (key_scan="1110" and keycol="1011") then key_val<=2;
elsif (key_scan="1110" and keycol="0111") then key_val<=3;
elsif (key_scan="1101" and keycol="1110") then key_val<=4;
elsif (key_scan="1101" and keycol="1101") then key_val<=5;
elsif (key_scan="1101" and keycol="1011") then key_val<=6;
elsif (key_scan="1101" and keycol="0111") then key_val<=7;
elsif (key_scan="1011" and keycol="1110") then key_val<=8;
elsif (key_scan="1011" and keycol="1101") then key_val<=9;
elsif (key_scan="1011" and keycol="1011") then key_val<=10;
elsif (key_scan="1011" and keycol="0111") then key_val<=11;
elsif (key_scan="0111" and keycol="1110") then key_val<=12;
elsif (key_scan="0111" and keycol="1101") then key_val<=13;
elsif (key_scan="0111" and keycol="1011") then key_val<=14;
elsif (key_scan="0111" and keycol="0111") then key_val<=15;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
clk_div<=clk_div+1;
end if;
clkd<=clk_div(6);
end process;
process(clkd)
begin
if rising_edge(clkd) then
if key_scan="1110" then key_scan<="1101";
elsif key_scan="1101" then key_scan<="1011";
elsif key_scan="1011" then key_scan<="0111";
elsif key_scan="0111" then key_scan<="1110";
else key_scan<="1110";
end if;
end if;
keyrow<=key_scan;
end process;
process(key_val)
type seg7 is array(0 to 15) of std_logic_vector(6 downto 0);
constant seg_val:seg7:=("1111110","0110000","1101101","1111001", "0110011","1011011","1011111","1110000",
"1111111","1110011","1110111","0011111",
"1001110","0111101","1001111","1000111");
begin
led_out<=seg_val(key_val);
end process;
a<='1';
end Behavioral;
Exp5. VHDL code for Elevator FUNCTIONS using FPGA kit.
entity elevator is
Port ( keyrow : out std_logic_vector(3 downto 0);
keycol :in std_logic_vector(3 downto 0);
a:out std_logic;
clk : in std_logic;
led_out : out std_logic_vector(0 to 6));
end elevator;
architecture Behavioral of elevator is
signal key_val,cur_flr:integer range
signal key_hit:std_logic;
signal key_scan:std_logic_vector(3 downto 0);
signal clk_div:std_logic_vector(22 downto 0);
signal clkd,flr_clk:std_logic;
begin
process(keycol)
begin
case keycol is
when "1110"=>key_hit<='1';
when "1101"=>key_hit<='1';
when "1011"=>key_hit<='1';
when "0111"=>key_hit<='1';
when others=>key_hit<='0';
end case;
end process;
process(key_hit)
begin
if rising_edge(key_hit) then
if (key_scan="1110" and keycol="1110") then key_val<=0;
elsif (key_scan="1110" and keycol="1101") then key_val<=1;
elsif (key_scan="1110" and keycol="1011") then key_val<=2;
elsif (key_scan="1110" and keycol="0111") then key_val<=3;
elsif (key_scan="1101" and keycol="1110") then key_val<=4;
elsif (key_scan="1101" and keycol="1101") then key_val<=5;
elsif (key_scan="1101" and keycol="1011") then key_val<=6;
elsif (key_scan="1101" and keycol="0111") then key_val<=7;
elsif (key_scan="1011" and keycol="1110") then key_val<=8;
elsif (key_scan="1011" and keycol="1101") then key_val<=9;
elsif (key_scan="1011" and keycol="1011") then key_val<=10;
elsif (key_scan="1011" and keycol="0111") then key_val<=11;
elsif (key_scan="0111" and keycol="1110") then key_val<=12;
elsif (key_scan="0111" and keycol="1101") then key_val<=13;
elsif (key_scan="0111" and keycol="1011") then key_val<=14;
elsif (key_scan="0111" and keycol="0111") then key_val<=15;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
clk_div<=clk_div+1;
end if;
clkd<=clk_div(6);
flr_clk<=clk_div(22);
end process;
process(clkd)
begin
if rising_edge(clkd) then
if key_scan="1110" then key_scan<="1101";
elsif key_scan="1101" then key_scan<="1011";
elsif key_scan="1011" then key_scan<="0111";
elsif key_scan="0111" then key_scan<="1110";
else key_scan<="1110";
end if;
end if;
keyrow<=key_scan;
end process;
process(flr_clk)
begin
if rising_edge(flr_clk) then
if(not(key_val=cur_flr)) then
if(key_val>cur_flr) then cur_flr<=cur_flr+1;
else cur_flr<=cur_flr-1;
end if;
end if;
end if;
end process;
process(key_val)
type seg7 is array(0 to 15) of std_logic_vector(6 downto 0);
constant seg_val:seg7:=("1111110","0110000","1101101","1111001",
"0110011","1011011","1011111","1110000",
"1111111","1110011","1110111","0011111",
"1001110","0111101","1001111","1000111");
begin
led_out<=seg_val(cur_flr);
a<='1';
end process;
end Behavioral;
